1. Field of Invention
Exemplary embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a plurality of transistors and a method of manufacturing the same.
2. Description of Related Art
A semiconductor device includes transistors that have different sizes and various electrical characteristics. For example, a flash memory device has low voltage transistors and high voltage transistors, different from each other, formed in a peripheral region thereof. The operation of low voltage transistors is controlled with a lower driving voltage than high voltage transistors. Thus, a method of stabilizing the operation of low voltage transistors has been developed. Particularly, a method of ensuring operating stability of low voltage transistors that have high leakage current characteristics due to their narrow width has been developed.
FIG. 1 is a graph illustrating drain current Ids in response to gate voltage Vgs of NMOS transistors having different widths. As shown in FIG. 1, an NMOS transistor having a relatively narrow width has high leakage current characteristics such as a current hump.
In general, in order to improve leakage current characteristics, impurities for controlling a threshold voltage are implanted into an active region in which a narrow transistor will be formed. However, concentration of the impurities for controlling a threshold voltage at the edges of the active region may be reduced in subsequent processes. Hereinafter, the reduction in concentration of the impurities for controlling a threshold voltage at the edges of the active region will be described in detail by exemplifying an NMOS transistor having a narrow width.
When an NMOS transistor has a narrow width, an impurity for controlling a threshold voltage such as Boron is implanted into an active region of a semiconductor substrate in which the NMOS transistor will be formed, so as to improve leakage current characteristics. An isolation region of the semiconductor substrate is subsequently etched to form a trench. In order to eliminate damage during an etch process of forming the trench, the surface of the trench is oxidized to form a side-wall oxide layer. During the process of forming the side-wall oxide layer, the boron implanted into the edges of the active region is separated from the edges of the active region (that is, boron segregation occurs). As a result, boron concentration at the edges of the active region becomes lower than at the center of the active region. After the side-wall oxide layer is formed, the trench is filled with an insulating material to form an isolation layer that separates the active region. A gate insulating layer and a gate are sequentially formed on top of the active region, and impurities for forming source and drain regions are implanted into the active region on both sides of the gate. The gate insulating layer and a gate conductive layer may be etched by using an isolation mask pattern for forming a trench as an etch barrier after they are formed on the semiconductor substrate before the trench is formed.
As described above, during the process of forming the side-wall oxide layer, the concentration of the impurities (e.g., boron) for controlling a threshold voltage may become lower at the edges of the active region than at the center of the active region. Accordingly, a parasitic transistor that has a low threshold voltage is formed at the edges of the active region than in the central portion of the active region. This parasitic transistor causes leakage current. In order to avoid deterioration of leakage current characteristics caused by the parasitic transistor, a method of additionally implanting impurities for controlling a threshold voltage through a mask that opens, for example, only a low voltage transistor region (e.g., a low voltage NMOS transistor region) that has a narrow width and high leakage current characteristics has been developed. However, this method has limitations in controlling deterioration of leakage current characteristics.